VLSI Architecture for Efficient Lifting-Based Forward and Inverse DWT

The wavelet transform is denoted by ‘WT’ gained wide-ranging approval in processing signal and in compressing image. A 2D analysis must be implemented to use WT for processing the image. Such powerful signal analysis technique can be implemented for non-stationary data using Lifting architecture for the Discrete Wavelet Transform (DWT). Since high speed implementation with low latency is a demanding task, so in this work, separable pipelining architecture is proposed for rapid computation for twodimensional one, discrete wavelet transform in lifting-based and by appropriate designing and also well transfer of the information among the two 1-D ‘DWT filters’, the small latency is achieved. In this article, separable pipelining architecture is also proposed for Inverse discrete wavelet transform (IDWT) which is based on inverse lifting scheme. Verilog HDL is used as a programming language to implement the above architectures and their simulation results are also presented.